Standard cell integrated circuit design involves several steps such as system-level design, design description conversion/verification, logic synthesis, and physical design. System-level design involves creating a behavioral, or functional specification, which may utilize a variety of languages and tools such as C/C++ models, Transaction Level Models (TLM), etc. The design description conversion/verification process, commonly known as register transfer level (RTL) design and verification, converts the functional specification into a description that describes the behavior of the electronic circuit at a register level on a per clock cycle basis. This process involves verifying a compiled version of the design description to ensure proper design behavior.
The logic synthesis stage involves using a standard cell library to transform the RTL design into a technology-dependent gate level netlist that includes standard cell instances and port connection information. The physical design process uses the gate level netlist to place standard cell instances on a design floorplan and route the design by placing wire segment objects to connect the standard cell instances according to connection data such as the port connection information. The design floor plan is typically based upon a semiconductor process technology corresponding to the standard cell library used to create the design.
Today's semiconductor process technologies use metal layers in a semiconductor wafer to connect the standard cell instances according to the routing results from the physical design stage. A semiconductor wafer's “first” metal layer, referred to as a “metal 1 layer,” also includes power rails that run in parallel to power the standard cell circuitry. As such, the place and route design tool typically routes connections around these power rails that, in turn, creates routing congestion areas, or “hot spots,” on the metal 1 layer from a high concentration of routing connections.